Static random access memory ("SRAM") systems are commonly used to store digital information in a computer system. Such memory systems are static in that information is stored in a plurality of latch-type core cells, without a need to dynamically refresh a store charge (as is the case for dynamic random access memory systems). Because there is no refresh cycle, SRAMs are relatively fast, with access times in the 12 ns to 15 ns range, or less.
FIG. 1 depicts an SRAM system 2 that typically is fabricated on an integrated circuit ("IC") chip. Generally system 2 includes several blocks, e.g., elements 4, 6, 8, 10, of storage units, wherein each block includes a plurality of latch-type memory cells. (Of course, fewer or more than four blocks may be present.) The individual core memory cells comprising each block are arrayed in addressable rows and columns, for example, 128 rows and 256 columns. Thus, for the configuration of FIG. 1, where four blocks are present, each block could contain 32 rows and 256 columns of cells.
To address a given memory cell within a block, system 2 provides row and block decoder logic 12 (for decoding a desired row address and block), and also provides column decoder logic 14 (for decoding a desired column address). Control logic 16 receives various control signals such as chip enable (CE), write enable (WE) and output enable (OE), which signals are coupled to the memory array blocks, e.g., 4, 6, 8, 10. These memory blocks also receive a block select (BK) signal and a word line select (WL) signal from row and block decoder 12.
Data to be written or stored within one or more memory cells are received by an input buffer 18, and then passed onto the desired memory cells within the blocks of memory via a write bit line. Reading information from a desired memory cell is accomplished by addressing that cell's row and column, and by coupling the cell to a sense amplifier 20. Sense amplifier 20 senses whether a "1" or a "0" is stored within the addressed cell, and provides the proper "0" or "1" output signal to an output buffer 22. The output port of buffer 22 provides a data output signal that is coupled to an I/O buss.
Conventionally, sense amplifier 20 is an analog device that receives a pair of differential analog input signals from complementary bit lines coupled across the memory cell being read. Such analog sense amplifiers function similarly to an analog differential amplifier. When the voltage difference between the sense amplifier input signals is sufficient in magnitude, the sense amplifier will output a "0" or a "1" signal, representing the data stored within the accessed memory cell. Partially because they can detect the proper "0" or "1" state of the stored data from differential signals that need not transition from full "0" to "1" values (or vice versa), analog sense amplifiers can function rapidly. Unfortunately, because analog sense amplifiers are very susceptible to design changes that can affect the sense amplifier trip point, in general, they cannot be used in retargetable SRAM systems.
A goal of modern SRAM design is that the system be retargetable. By retargetable it is meant that the design, once written in various software design files, may be duplicated using different fabrication processes and/or different technologies. For example, a present design based upon a minimum metal-on-semiconductor ("MOS") transistor gate width of say 0.8 .mu.m may in the future be capable of implementation using newer 0.5 .mu.m technology.
In a retargetable SRAM design, it would suffice to input to the software files different scaling information. For example, if a MOS transistor of unit dimension size previously used 0.8 .mu.m geometry, it should suffice to instruct the general technology software files that the unit dimension is now 0.5 .mu.m, whereupon new fabrication masks and layout will be generated. Ideally the resultant scaled-down IC SRAM system should function without substantial redesign.
Unfortunately, the presence of analog sense amplifiers 20 makes system 2 essentially non-retargetable. For example, implementing the sense amplifiers with differently sized MOS transistors and/or simply coupling the sense amplifier to differently sized MOS transistors can affect the trip point voltage at which the sense amplifier changes state. While possibly the sense amplifier and/or components to which it is coupled could be redesigned, having to do so is unacceptable in a truly retargetable SRAM system design.
Although analog sense amplifiers do not contribute to a retargetable SRAM memory system, their presence at least tends to prohibit excessive crowbar current when operating voltage is first coupled to the system ("power-up"). As used herein, "crowbar current" refers to DC current that may be drawn in a system during power-up.
What is needed is a method of implementing a retargetable SRAM memory system. Preferably such method should avoid the use of analog sense amplifiers but should nonetheless provide rapid signal sense capability. Further, such method should minimize crowbar current at system power-up.
The present invention provides such a method and apparatus.